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CST: 14/11/2019 00:05:11   

Tom Fitzpatrick to Receive Accellera Systems Initiative Technical Excellence Award

267 Days ago

Fitzpatrick of Mentor, a Siemens Business, will be honored for his contributions to Portable Stimulus, UVM, SystemVerilog and more at DVCon U.S. 2019

ELK GROVE, Calif., Feb. 19, 2019 (GLOBE NEWSWIRE) -- Accellera Systems Initiative (Accellera) announced today that Tom Fitzpatrick, Vice Chair of the Portable Stimulus Working Group and member of the UVM Working Group, is the recipient of the eighth annual Accellera Technical Excellence Award.  The award was established to recognize the outstanding achievements of an individual among Accellera’s working group members and their significant contributions to the development of its standards.

Fitzpatrick, a noted verification evangelist, will be presented with the award at DVCon U.S. on Monday, February 25 during the Accellera Day luncheon from 12:00-1:30pm at the DoubleTree Hotel in San Jose, California.  He will be recognized for his many years of dedication to the advancement of Accellera standards.   He has been a key contributor to the evolution and adoption of the Universal Verification Methodology (UVM) standard, Verilog and SystemVerilog standards and the development and launch of the Portable Test and Stimulus Standard 1.0 (PSS).

“Tom is a passionate verification technologist who has been at the forefront of ushering new languages and methods into industry practice for decades,” stated Martin Barnasconi, Accellera Technical Committee Chair.  “He has been involved since the very early days of Verilog, guiding it to SystemVerilog within Accellera.  He helped to bring an industry-unifying verification methodology to the global community of verification engineers, now known as UVM.  In recent years, Tom has been one of the key drivers behind the development of the Portable Test and Stimulus Standard (PSS). Tom’s contributions to the advancement of industry standards and his technical leadership need to be recognized. He is well-deserving of the 2019 Accellera Technical Excellence Award,” Barnasconi added.

"I am honored to receive this award from Accellera, and humbled to be recognized for doing work that I think is very important for our industry,” said Fitzpatrick, Strategic Verification Architect at Mentor, a Siemens Business.  “I have been blessed to work for many of the companies responsible for the creation and advancement of Accellera standards, including Mentor, which has helped pioneer portable stimulus technology since 2004, and led its standardization effort that began in 2014. I am gratified to have played a part in advancing the state of the art in verification over the years, and look forward to continued progress and collaboration with colleagues and peers throughout the industry.”

Fitzpatrick has been a member of Accellera since its merger with the Open SystemC Initiative in 2011 and has participated in numerous working groups.  He has been the Vice Chair of the Portable Stimulus Working Group since its inception in 2015.  He participated in the core group that developed the Verilog standard more than 25 years ago and as a result, served as Chair of the IEEE 1364 Working Group.  He has been a long standing champion of UVM and participated in the IEEE 1800.2 Working Group in its infancy. 

He began his career at Digital Equipment Corporation as a hardware and chip designer, later moving into EDA, and has worked for several startup companies as well as each of the “big 3” EDA companies. Fitzpatrick is also currently Technical Program Chair for DVCon U.S. 2019.  He was General Chair of DVCon in 2009 and has been the Editor of Verification Horizons publication since its beginning.  

He holds a bachelor’s and master’s degree in both computer science and electrical engineering from the Massachusetts Institute of Technology.

About the Accellera Technical Committee
Accellera's Technical Committee oversees 13 active working groups that produce effective and efficient Electronic Design Automation (EDA) and Intellectual Property (IP) standards for today’s advanced IC designs. Participants include member companies and industry contributors. Technical contributors typically have many years of practical experience with IC design and developing and using EDA tools. For a list of Accellera working groups, please click here.

About Accellera Systems Initiative
Accellera Systems Initiative is an independent, not-for profit organization dedicated to create, support, promote and advance system-level design, modeling and verification standards for use by the worldwide electronics industry. The organization accelerates standards development and, as part of its ongoing partnership with the IEEE, its standards are contributed to the IEEE Standards Association for formal standardization and ongoing change control. For more information, please visit www.accellera.org. Find out more about membership. Follow @accellera on Twitter or to comment, please use #accellera. Accellera Global Sponsors are: Cadence; Mentor, A Siemens Business; and Synopsys.

About DVCon U.S.
DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. In response to global interest, in addition to DVCon U.S., Accellera also sponsors events in China, Europe and India.  For more information about DVCon U.S., please visit www.dvcon.org. Follow DVCon on Facebook https://www.facebook.com/DvCon or @dvcon_us on Twitter or to comment, please use #dvcon_us.

Accellera, Accellera Systems Initiative, and DVCon and are trademarks of Accellera Systems Initiative Inc. All other trademarks and trade names are the property of their respective owners.

For more information, contact:
Barbara Benjamin
Public Relations for Accellera Systems Initiative
Phone: +1 503 209 2323
Email: barbara@hipcom.com 

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